1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for using an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip in order to speed up subsequent operations on the layout.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
A layout for a semiconductor chip is often stored in a standard hierarchical format, such as GDSII stream format. For example, FIGS. 1A, 1B and 1C illustrate how a layout, T, can be composed of a sub-cell A and a sub-cell B, wherein the sub-cell A further includes a sub-cell C. FIG. 1A illustrates a nodal representation of this hierarchy, while FIG. 1B illustrates a corresponding graphical representation.
FIG. 1C presents a specification of the layout in code form. In this form, the layout, T, includes a reference list. This reference list includes a reference to cell A along with an associated transformation, TA, and a reference to cell B along with an associated transformation, TB. Similarly, the layout for cell A includes geometrical features associated with cell A along with a reference cell C. This reference to cell C is accompanied by a transformation of cell C with respect to A, TCA. The layouts for cell B and cell C include geometrical features associated with cell B and cell C, respectively.
Representing a layout in a hierarchical format can cause problems for various operations related to production of a semiconductor chip, such as die-to-database inspection of a mask, defect analysis on a wafer or a mask, verification of a layout against a simulated silicon image of the layout, and proximity effect correction during mask writing.
During any of these operations, interactions between nodes within the hierarchical representation can cause erroneous results. This problem can be remedied by collapsing the hierarchy down into a single monolithic layout before performing the operations. Unfortunately, this technique can be prohibitively slow because the operations must be applied to the entire monolithic layout, even though many of the cells in the layout many be repeated.
What is needed is a method and an apparatus for performing a computational operation on a hierarchical representation of a layout without performing the computational operation over the entire layout, and without the above-described problems associated with using a hierarchical representation.
One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
In one embodiment of the invention, the layout includes features on the semiconductor chip, or features on a mask that is used to create the semiconductor chip.
In one embodiment of the invention, converting the representation into the instance-based representation involves considering how interactions with other nodes affect each node, and considering how environmental attributes specified in the layout affect each node.
In one embodiment of the invention, the layout includes a hierarchy of nodes, wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
In one embodiment of the invention, the system additionally collapses the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes (sibling nodes) in the hierarchy.
In one embodiment of the invention, performing the further processing involves performing a die-to-database inspection. This is accomplished by performing an initial die-to-database inspection of an image generated from a node instance, and then performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.
In one embodiment of the invention, performing the further processing involves performing verification on the layout to verify that a simulated silicon image of a node conforms to a layout of a node. In a variation on this embodiment, the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.
In one embodiment of the invention, performing the further processing involves performing proximity effect correction while generating a mask to be used in fabricating the circuit. In this way, a correction to be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.
One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. The system then converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. Next, the system performs a defect analysis by locating defects, and then using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.